Tuesday, February 12, 2013

Picking Dies Off of Dicing Tape

Typically providers of dicing tape provide a specification sheet on material but rarely does it include any information on pick force required to remove the die from the tape.  In a Journal of Solid Mechanics and Material Engineering article in 2010 LINTEC Corporation published a study of pick force versus peel strength.  In it a way to approximate pick force required was introduced.

Study on Peeling Behavior

Formula for Determining Pick Force Required

The study concluded that there was a correlation, but the study focused on die attached adhesives in sheet format not in dicing tapes themselves.  It does beg the question though can dicing tape pick force be determined by peel strength.  While this paper provides no definitive answer I may be able to comment on this in a future posting. 

Friday, February 8, 2013

Laser Dicing

Laser Dicing is reported to have a number of advantages over blade dicing.

     - Faster cutting speed versus blade dicing
     - Less Backside Chipping
     - Narrower Kerf (Distance between chips(dies))
             o More product per wafer
     - Many laser singulation technologies do not use water

Laser Dicing Singulation of Silicon
Stealth Dicing Article
Chip Scale Review Article (pg.26)

What is often overlooked is the role of dicing tape in laser dicing.  Laser dicing produces considerably more heat than a blade dicing process.  This is one of the reasons why Synova developed the waterjet full ablation laser dicing system.

Traditional dicing tapes will heat and melt under the temperature generated by the laser and each type of laser dicer requires a different tape depending on the process.
Waterjet Laser Dicing: Porous tape or high adhesion tape.

Full Ablation (Full-Cut) Dicing: Tape which can withstand the energy generated by the laser.

Stealth Dicing: Expandable tape (frontside stealth dicing) or a transparent one for stealth dicing from the backside.

The advantages of laser dicing are compelling; lower CoO through faster throughput, more devices per wafer, and potentially increased die strength, but one must not neglect the role dicing tape plays in this process as laser dicers need to be paired with the right tape to work well.

If you have questions please leave a comment.

Tuesday, February 5, 2013

Scribe and Break Process

There are many varying singulation technologies available and while on the surface singulation of wafers seems straight forward achieving singulation with minimal backside chipping can be quite challenging.  As previously noted Dice Before Grind can be used to minimize backside chipping and improve die strength versus the industry standard blade dicing, but other techniques are available and can make sense depending on the device being singulated.

Scribe and Break is a process that does not rely on cutting through the wafer but creating either an internal fracture in the case of Laser Stealth Dicing or dicing a few microns into the top side with a blade or a laser and using an expansion process to expand the wafer so that in breaks along the scribed line or use an anvil to create the same result.  Below is an article on the process.

Critical to the success of this process is the tape.  The tape itself requires even expansion for two purposes.  The first is to allow the dies to singulate.  The second is to allow the kerf width (distance between dies) to be consistent in both X and Y directions for subsequent processing.  The link below can help recommend a dicing tape for a scribe and break process.

If you have any questions then please feel free to post questions below.

UV Dicing Tape Scribe and Break Tape

Friday, February 1, 2013

TAIKO Process. Is it viable for TSV production?

TAIKO is a process where a thick wafer is thinned in the center to allow backside development. 

The semiconductor industry is facing a major challenge to increase the speed of certain core technologies without increasing costs to consumers.  At the Flash Memory Conference last year one of the topics was on achieving higher speeds for DRAM in order to support next generation technologies.  The problem is the speed limits of wire bonding have been reached and subsequent technology improvements will require the use of TSV (Through Silicon Vias).

The issue with TSV is one of yield and cost.  The biggest issue today is how to handle thin ground wafers in order to develop the trenchs and backside connection points needed to enable a stack of DRAM dies using TSV.  The common approach is to attach a support to the wafer and then thin the backside.  Every approach used to form the vias relies at some point on handling thinned wafers and the support is required in all process flows.  Debonding and removing the support is problematic which effects yield.  In addition the cost of the support materials is not cheap and adds increasing cost to devices that are marketed to end users that are cost sensitive.

A potential solution is the TAIKO process, but can the TAIKO process be used for TSV production?  The TAIKO process (illustrated below) has one major issue.  It does not protect the circuit side during processing.
Below is a link to a presentation for a way to overcome this issue potentially.
TSV H-WSS Alternative Carrier Less Processing

TSV Update Disco October 2012

On the left is a picture of a wafer coated with a protective substance and TAIKO ground.  With no carrier it does not require additional capital investment to remove a carrier or apply an expensive bonding material.  This could be the path forward to enable higher yield lower cost TSV.

Once TSV are formed with TAIKO wafer dicing tape mounter becomes critical.  The reason is the large lip makes it near impossible to mount the dicing tape to the wafer.  A new wafer mounter from LINTEC the RAD-2512F/12 can solve this issue.

TAIKO TSV Wafer Mounter

If the new coating can resist the steps required for various backside development and be used in conjunction with a wafer mounter designed to mount tape to a TAIKO wafer it is possible TAIKO's lower CoO will help enable the next generation of devices.

Thursday, July 5, 2012

New Article on Low-k Material Dicing

On Tuesday my post included information on dicing Low-k wafers; however on Thursday I discovered additional information presented in Semicon China in 2012.  I will visit ALSI at Semicon West 2012 to confirm the information contained and to find out more about their technology.

Basically it is a multi-beam technology which will allow for a clean singulation of the top layers.  Subsequent singulation can be performed using a standard dicing blade.

The question then becomes which mechanical dicing blade to use and how deep to cut into the tape.  As stated in a previous post dicing tape selection is more than simply looking for a tape with high peel strength pre-UV and a low peel strength tape post-UV.  Peel strength is a metric which does not tell the whole story.  The missing aspects will be the modulus of the tape and tack testing results.

If you would like to learn more about this then please contact me and I would be happy to discuss both aspects and how they relate to dicing tape selection.

Tuesday, July 3, 2012

Dicing Low-K Materials

Dicing Low-k materials is challenging.  The conventional approach using one or multiple dicing blades created issues of front side chipping or layers would peel away causing device failure.  In an article in 2004 Synova proposed a full cut approach using a laser cooled by water.

Below is an example of the results which are quite impressive indeed on a low-K wafer.

ADT and Disco both developed approaches whereby the wafer is grooved with a laser and then the wafer is diced using a mechanical blade.

Low-k materials requires a new approach to singulation.  What is often missed in discussions on singulation is dicing tape.

Dicing tape is more than a "sticky support" for a water jet application the wrong dicing tape will cause dies to fly off and for the groove and dice solution dicing tape plays a critical role as the wrong tape could cause backside chipping or die fly off.  If you have any questions regarding which tape might be right for your process please contact me.

DBG Process

The conventional dicing process consists of mounting a wafer on to a medium (wax or tape) and then connecting either to a hoop ring (set of concentric expansion rings) or a ring frame (either stainless steel or plastic) and then dicing through the material.  In the conventional process the dicing process is the process of singulation where a chip or die is separated from the wafer.  Their are issues with this process which affect yield.

One of the largest of these issues is backside chipping.  Backside chipping has many potential root causes but the effect is the same lower die strength.
 A Study on Chip Thinning Process for Ultra Thin Memory Devices (Toshiba)
Link to the Toshiba White Paper

The chart above is a test on dies ranging from 10um to 25um thick.  The results clearly demonstrate that backside chipping (conventional) reduces die strength.  Reduced die strength may result in failure during subsequent steps in ultra-thin chips.  So what is the answer?

One potential answer is DBG (Dice Before Grind).  This process was developed in 1999 by Toshiba and two suppliers stepped up to deliver the solution Disco Corporation and LINTEC Corporation.
1999 DBG Press Release

The above illustration shows the steps in the DBG process.  Disco supplies the half-cut dicer (blades) and grinder (grind wheels) and LINTEC supplies the back grind tape laminator (back grind tape) and wafer mounter (pick-up tape).  Links to all of the products are listed below.

Back Grind Tape Laminator and Mounter
Half-Cut Dicer and Grinder

Investing in new systems may not be cost effective for smaller companies so there are vendors who offer to process DBG wafers.  Contact me for a list of companies who can supply this service.  In addition this process can be done using manual equipment on a smaller scale.  I can not publish the results or technique here but it there has been significant data collected using semi-auto Disco and LINTEC equipment and if you contact me I would be happy to help design a more cost effective process for lower wafer volumes.

The decision to use the DBG process really depends on the thickness of the die, the package design, and the effect chipping (front side and back side) have on device performance.  DBG may not be for every application, but for applications requiring ultra-thin strong dies it will increase die strength and ultimately positively impact yield.